JRC-1

JRC-1, or Josh’s Retro Computer 1, is the first in what will be the new JRC series of SBCs. It is my third SBC project and is the successor to COLE-1 and COLE-2.

Unlike it’s predecessor, JRC-1 removes the complication of on-board video, and instead adds an expansion bus through which video can be added later. The intention is to make the base design less complex and easier to design and debug. It will also be going back to its retro roots, with more through-hole components and a full 5V design.

This project is in its early planning stages. At the moment, the planned specs will be:

  • 65C816 CPU, initially at 4 MHz with plans to increase down the road
  • 1 MB of RAM
  • 256 KB of ROM, capable of in-system reprogramming (W29C020)’
  • CPLD glue logic (JIGL – JRC Integrated Glue Logic)
  • Two 65C22 VIAs
  • Two DB-9 serial ports (NXP 28L92 dual UART)
  • Real-time clock
  • SD card for loading the OS and applications
  • Three expansion slots, accessed through a VIA