Expansion Bus Woes

When I first start planning the JRC-1, my main goal was to produce a simple base design with which I could experiment with more advanced features down the road. Something akin to the original IBM PC, except with a 65816. Meeting that goal meant I needed some sort of expansion bus.

The Design

Before I started any design work I ran my original plans by the folks at the 6502 forums. There are a lot of very smart people there who have experience with these things, and I trust their advice. The recommendation was that I not bring the system buses out of the slots. Instead, I should create an expansion bus behind a 6522 VIA.

After a few iterations I settled on a bus design. My bus looked very similar to the typical bus you might find on a RAM or ROM chip. It has six address lines, eight data lines, a R/W signal, a slot enable, and an I/O strobe. A pulse on the I/O strobe signals the card to perform a transaction. This design was chosen to interface to as many available peripheral chips as possible with minimal additional logic. It also fits on a single VIA, so I could test the design on COLE-1+.

The Experiment

At this point I need to mention that the deal-breaker application for any expansion bus is that I can create a video card for it. Sp. I adapted the TIVI code that I wrote for the TinyFPGA board to run on my ULX3S and hooked it up to COLE-1+. The results were….less than encouraging.

The whole setup was terribly unreliable. Sustained writes would frequently result in missed or duplicated bus transactions and thus garbled frame buffer data. Hooking up a scope did not reveal anything wrong at the signal level. The signals were very clean, and there was very little ringing or cross-talk. Manually slowing things down in code did not help at all, either.

I have spent many hours in the past week trying to fix this issue without success. My working theory is that the relatively high rise/fall times on the strobe line may be problematic. At 50 ns it might very well be causing metastability issues inside the FPGA. Given enough time I could probably make this work, but my frustration level has reached maximum.

Moving Forward

After a lot of thought I’ve come to realization that my expansion bus is turning into the kind of project-killing feature that doomed COLE-2. The irony here is that I was trying to avoid this exact issue by having expansion slots in the first place!

If I want JRC-1 to actually be finished and built, then I need to move past this. Instead of trying to come up with the perfect design on my first try, I’m just going to build what I really want, and if it is unstable, or fails outright, then I learn from that and design a better version.

And so I have decided to go with an ISA-style bus that provides access to buffered versions of the main board buses. This should work fine for at least a couple of MHz, and anecdotal evidence from folks using RC2014 and ISA backplanes suggests I may be able to hit 8 MHz without too much trouble. The only way to tell for sure is to build the dang thing and see what happens!


  1. Hello Mr. Thompson.

    I have recently rediscovered my early years of personal computing by dusting off my second computer, an Apple IIe, with the Commodore PET 2001-8 being the first. I still have both from some 30+ years ago.

    I am trying to use ADTPro to transfer programs and disk images from the Mac Mini to the Apple IIe but the speed is very slow via the cassette port. Unfortunately, buying an old Apple SSC is difficult due to the high cost. I can across your design on GitHub and have made a few PCBs and started to populate the first. While waiting for the GAL and OSC to arrive, I am turning my attention to the firmware. Since there is no DIP switches on this design and the initial configuration is undetermined, do you have an updated SSC firmware image that have the initial configurations patched that I may have please? If not, perhaps some pointer as to where the 341-006A ROM should be patched would be gratefully received.

    I have only last week bought an Apple IIGS. When I finally got the SSC going, I would visit again for the very interesting XGS project!

    Thank you for generously allowing the unrestricted use of your SSC design!


    Kwong Li
    London, UK

    1. I never got around to patching the firmware because I couldn’t get the design fully working; I could send and receive characters manually in the system monitor, but ADT Pro always timed out when I tried using it. I think the issue might have been bad ACIAs (note that you can’t use new WDC ones as they have a hardware bug). At some point I’m going to try just designing a new version of the board that uses a CPLD to emulate the ACIA, thus alleviating the need to find working ones.

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